The present invention relates to flash fuse element memory cells, and more particularly to non-volatile flash fuse memory cells having provisions for margining, testing and stressing.
A flash memory is a type of non-volatile memory cell that is electrically reprogrammable. Flash memories are used in various electronic systems such as cellular telephones, personal data assistants (PDA), and notebook computers. The flash memories typically are used for configuration bit storage, redundancy information, non-volatile program, read, and erase algorithm parameter setting, maker and manufacturing identification, and voltage reference and bias trimming. The flash memories typically use programmable fuse elements. Conventional fuse elements are single ended sensing, uncontrolled current differential sensing or with reduced margin.
The present invention provides a memory device comprising first and second fuse elements and a latch coupled to the fuse elements for storing the contents of the first and second fuse elements. In another aspect, the latch includes a differential amplifier. In another aspect, the fuse elements include split gate memory cells.
In one aspect of the present invention, the memory-device comprises first and second margining circuits coupled in parallel to the first and second fuse elements, respectively. In another aspect, margining circuits comprise transistors that have electrical characteristics similar to the control gate and floating gate of a split gate memory cell of the fuse elements. In another aspect, the margining circuits use current offset to check margin.
In one aspect of the present invention, an equalization network is coupled between the first and second fuse elements to equalize a control voltage applied to the first and second fuse elements.
In one aspect of the present invention, a resistor-capacitor filter is coupled to the gate of the split gate memory cell of the fuse elements.
In one aspect of the present invention, a clamp is coupled to the control gate of the fuse elements. In another aspect of the present invention, the clamp is operable during reads.
In one aspect of the present invention, a forcing circuit forces the fuse elements to a particular state.
In one aspect of the present invention, the control gate of one of the first and second fuse elements is set to a reference voltage. A reference value of the control gate of the other of the fuse elements is compared by the corresponding latch of the memory cell.
In one aspect of the present invention, a signal that is applied to the memory cells is set at a voltage to stress the memory cells.
In one aspect of the present invention, a plurality of memory devices may be coupled together.